report_05-07-2025_03-03-16.html

[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Div_144'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'Div_144', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Div'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-1' pid=2379850 parent=2378920 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5d84fabd8650 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.115s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2157s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2159s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 29.79017710275709 MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18700095 bytes MEM: Free's : 27 free's of 18700095 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-1: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 29.79017710275709 is higher than threshold 0.5

[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Div_157'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'Div_157', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Div'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-1' pid=2379864 parent=2378788 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x647e07d8ed20 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.93s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2008s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2010s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 27.942498479771785 MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18703423 bytes MEM: Free's : 27 free's of 18703423 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-1: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 27.942498479771785 is higher than threshold 0.5

[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Div_Const_6'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'Div_Const_6', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Div'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-1' pid=2379863 parent=2378283 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x601472287e30 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.141s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4245s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4248s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 59.07199322681382 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19188653 bytes MEM: Free's : 26 free's of 19188653 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-1: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 59.07199322681382 is higher than threshold 0.5

[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Div_173'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'Div_173', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Div'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-1' pid=2379855 parent=2378318 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x59b3e7d83fc0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.85s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1433s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1435s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 65.3736226725294 MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18763695 bytes MEM: Free's : 27 free's of 18763695 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-1: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 65.3736226725294 is higher than threshold 0.5

[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Div_Const_48'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'Div_Const_48', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Div'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-1' pid=2379865 parent=2378270 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x623e9e787ff0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.106s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1936s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1938s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 65.21007623791704 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 100488109 bytes MEM: Free's : 26 free's of 100488109 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-1: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 65.21007623791704 is higher than threshold 0.5

[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Div_230'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'Div_230', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Div'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-1' pid=2379857 parent=2378264 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x6530eeb4c8f0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.10123s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.11013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.11028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.11048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.11061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.11081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.11100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.11125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.11138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.11152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.11169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.11182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.11197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.11219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.11235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.11246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.11265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.11280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.11295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.11314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.11327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.11338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.11355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.11415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.11429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.11447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.11461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.11474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.11490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.11506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.11521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.11544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.11556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.11569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.11585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.11602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.11615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.11634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.11646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.11662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.11681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.11700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.11701s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.11703s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 3.1729326171735983 MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18701691 bytes MEM: Free's : 27 free's of 18701691 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-1: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 3.1729326171735983 is higher than threshold 0.5

[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Div_201'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'Div_201', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Div'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-1' pid=2379854 parent=2378273 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x6103ffc2dbf0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.80s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.25892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.25921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.25938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.25951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.25970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.25984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.25996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.26014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.26027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.26039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.26053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.26065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.26078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.26097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.26108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.26121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.26138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.26151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.26165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.26185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.26202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.26217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.26233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.26244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.26259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.26275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.26288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.26300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.26316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.26327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.26345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.26359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.26372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.26384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.26398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.26410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.26427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.26444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.26459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.26473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.26493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.26494s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.26496s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 68.86834068709878 MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18704672 bytes MEM: Free's : 27 free's of 18704672 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-1: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 68.86834068709878 is higher than threshold 0.5

[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Div_236'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'Div_236', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Div'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-1' pid=2379871 parent=2378555 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5caba5e836e0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.106s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1807s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1810s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 18.85097112895592 MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18709280 bytes MEM: Free's : 27 free's of 18709280 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-1: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 18.85097112895592 is higher than threshold 0.5

[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Div_297'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'Div_297', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Div'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-1' pid=2379859 parent=2378986 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5cb99c1bf3e0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.108s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.42644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.42684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.42704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.42732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.42756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.42784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.42812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.42832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.42854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.42886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.42911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.42938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.42962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.42983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.43004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.43029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.43054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.43084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.43108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.43127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.43148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.43173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.43194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.43217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.43246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.43266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.43295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.43319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.43340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.43361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.43388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.43408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.43439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.43469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.43497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.43522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.43552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.43554s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.43557s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 3542.7385939330425 MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18796028 bytes MEM: Free's : 27 free's of 18796028 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-1: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 3542.7385939330425 is higher than threshold 0.5

[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Div_391'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'Div_391', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Div'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-1' pid=2379856 parent=2378352 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5d1b696d9a80 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.429s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1690s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1691s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 4.40181938764377 MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18699874 bytes MEM: Free's : 27 free's of 18699874 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-1: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 4.40181938764377 is higher than threshold 0.5

[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Div_Const_391'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'Div_Const_391', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Div'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-1' pid=2379862 parent=2379051 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5a39963636c0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.94s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1593s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1596s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 55.05820422541293 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18668804 bytes MEM: Free's : 26 free's of 18668804 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-1: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 55.05820422541293 is higher than threshold 0.5

[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Div_Const_295'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'Div_Const_295', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Div'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-1' pid=2379867 parent=2378276 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x59dfe1fb20c0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.77s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1698s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1700s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 1.3637512178074715 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18778285 bytes MEM: Free's : 26 free's of 18778285 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-1: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 1.3637512178074715 is higher than threshold 0.5

[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Div_95'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'Div_95', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Div'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-1' pid=2379870 parent=2378655 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x637853d98de0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.100s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.12631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.12679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.12707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.12725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.12752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.12776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.12794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.12812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.12834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.12852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.12872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.12890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.12908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.12930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.12954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.12977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.12995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.13014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.13029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.13050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.13068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.13091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.13107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.13126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.13147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.13166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.13185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.13200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.13220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.13239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.13262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.13279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.13299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.13315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.13335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.13355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.13381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.13399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.13421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.13443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.13464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.13465s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.13468s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 4.407995204715881 MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18699535 bytes MEM: Free's : 27 free's of 18699535 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-1: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 4.407995204715881 is higher than threshold 0.5

[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Div_52'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'Div_52', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Div'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-1' pid=2379869 parent=2378280 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x579909a5ab40 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.100s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1897s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1899s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 597.5955367104782 MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 21410461 bytes MEM: Free's : 27 free's of 21410461 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-1: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 597.5955367104782 is higher than threshold 0.5

[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Div_426'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'Div_426', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Div'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-1' pid=2379858 parent=2379184 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x588efaeeb6b0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.86s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5573s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5575s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 30.654635145070127 MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 19335554 bytes MEM: Free's : 27 free's of 19335554 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-1: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 30.654635145070127 is higher than threshold 0.5

[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Div_429'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'Div_429', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Div'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-1' pid=2379853 parent=2379218 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x55cc7ee5a700 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.69s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.49915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.49964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.49989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.50017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.50050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.50075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.50106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.50129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.50149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.50177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.50202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.50223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.50249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.50275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.50299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.50325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.50350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.50376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.50401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.50422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.50448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.50479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.50502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.50523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.50550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.50571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.50592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.50616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.50636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.50658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.50694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.50719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.50740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.50769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.50789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.50812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.50846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.50872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.50899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.50933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.50958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.50960s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.50963s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 13.967129783317667 MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 19334304 bytes MEM: Free's : 27 free's of 19334304 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-1: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 13.967129783317667 is higher than threshold 0.5

[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Div_440'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'Div_440', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Div'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-1' pid=2379860 parent=2378267 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5972cc633470 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.92s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1933s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1937s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 45984.66089664676 MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 21832694 bytes MEM: Free's : 27 free's of 21832694 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-1: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 45984.66089664676 is higher than threshold 0.5

[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Div_149'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'Div_149', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Div'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-2' pid=2381408 parent=2378822 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5fa34504bf90 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.159s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.13699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.13730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.13818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.13837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.13867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.13891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.13917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.13941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.13965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.13988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.14014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.14035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.14061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.14090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.14111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.14142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.14165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.14187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.14209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.14235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.14255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.14281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.14306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.14325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.14346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.14368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.14391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.14413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.14434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.14457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.14489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.14509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.14532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.14555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.14575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.14597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.14628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.14651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.14672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.14697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.14726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.14728s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.14732s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 57.02782271734467 MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18700263 bytes MEM: Free's : 27 free's of 18700263 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-2: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 57.02782271734467 is higher than threshold 0.5

[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Div_168'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'Div_168', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Div'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-2' pid=2381409 parent=2378753 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5c2eea186cc0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.123s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.9346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.9391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.9420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.9441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.9464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.9488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.9511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.9537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.9565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.9584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.9606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.9632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.9655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.9678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.9702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.9725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.9748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.9770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.9794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.9820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.9841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.9864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.9883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.9907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.10004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.10028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.10047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.10068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.10093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.10113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.10138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10192s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10195s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 16.064875997479028 MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18762855 bytes MEM: Free's : 27 free's of 18762855 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-2: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 16.064875997479028 is higher than threshold 0.5

[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Div_419'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'Div_419', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Div'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-2' pid=2381411 parent=2378489 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5c413e2cc120 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.117s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2283s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2285s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 69.8189141825946 MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18858594 bytes MEM: Free's : 27 free's of 18858594 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-2: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 69.8189141825946 is higher than threshold 0.5

[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Div_59'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'Div_59', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Div'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-2' pid=2381410 parent=2378420 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x63f66cb504d0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.71s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.18862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.18881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.18895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.18909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.18926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.18939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.18952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.18967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.18980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.18994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.19008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.19020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.19033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.19047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.19060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.19073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.19087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.19099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.19112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.19127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.19140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.19155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.19167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.19179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.19191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.19205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.19220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.19237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.19251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.19264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.19279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.19295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.19296s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.19298s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: inf MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 582833241 bytes MEM: Free's : 27 free's of 582833241 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-2: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of inf is higher than threshold 0.5

[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Div_355'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'Div_355', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Div'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-2' pid=2381569 parent=2378486 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x6020242eafb0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.112s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5981s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5984s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 30.099492911807783 MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18703423 bytes MEM: Free's : 27 free's of 18703423 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-2: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 30.099492911807783 is higher than threshold 0.5

[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Div_129'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'Div_129', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Div'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-2' pid=2381563 parent=2379119 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5fc00b018250 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.106s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5579s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5582s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 1.6238097880310383 MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18805593 bytes MEM: Free's : 27 free's of 18805593 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-2: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 1.6238097880310383 is higher than threshold 0.5

[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Div_Const_135'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'Div_Const_135', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Div'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-2' pid=2381631 parent=2379184 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x588efb039830 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.111s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.15073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.15119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.15143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.15170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.15205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.15228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.15254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.15278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.15307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.15329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.15354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.15383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.15403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.15428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.15453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.15474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.15499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.15522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.15544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.15565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.15595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.15625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.15645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.15671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.15693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.15714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.15740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.15760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.15784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.15811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.15835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.15853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.15876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.15896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.15919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.15945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.15972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.15991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.16019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.16044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.16069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.16071s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.16074s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 6.470182865364746 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19107117 bytes MEM: Free's : 26 free's of 19107117 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-2: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 6.470182865364746 is higher than threshold 0.5

[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Div_Const_438'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'Div_Const_438', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Div'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-2' pid=2381718 parent=2378283 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x6014722be560 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.70s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5546s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5548s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 55.8465915292451 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 21225069 bytes MEM: Free's : 26 free's of 21225069 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-2: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 55.8465915292451 is higher than threshold 0.5

[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Div_121'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'Div_121', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Div'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-2' pid=2381848 parent=2378986 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5cb99c1fe450 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.112s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.7719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.7749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.7770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.7789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.7812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.7836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.7858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.7875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.7894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.8003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.8022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.8042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8490s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8493s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 4.203575748623184 MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18725721 bytes MEM: Free's : 27 free's of 18725721 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-2: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 4.203575748623184 is higher than threshold 0.5

[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Div_71'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'Div_71', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Div'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-2' pid=2381955 parent=2379051 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5a39963a8350 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.98s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1752s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1754s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 1.2420210179544815 MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18700027 bytes MEM: Free's : 27 free's of 18700027 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-2: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 1.2420210179544815 is higher than threshold 0.5

[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Div_Const_39'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'Div_Const_39', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Div'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-2' pid=2381956 parent=2378920 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5d84fab39f60 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.100s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1585s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1588s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 20.721911401322156 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 22115245 bytes MEM: Free's : 26 free's of 22115245 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-2: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 20.721911401322156 is higher than threshold 0.5

[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Div_Const_18'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'Div_Const_18', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Div'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-2' pid=2382068 parent=2378276 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x59dfe1ff4b10 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.110s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2174s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2176s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.6352531942485857 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18759149 bytes MEM: Free's : 26 free's of 18759149 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-2: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 0.6352531942485857 is higher than threshold 0.5

[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Div_114'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'Div_114', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Div'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-3' pid=2382112 parent=2378267 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5972cc764480 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.78s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1653s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1655s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 76.48177497443476 MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18705977 bytes MEM: Free's : 27 free's of 18705977 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-3: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 76.48177497443476 is higher than threshold 0.5

[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Div_Const_310'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'Div_Const_310', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Div'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-2' pid=2382111 parent=2378352 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5d1b69633f00 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.109s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.15851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.15879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.15909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.15931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.15964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.15986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.16010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.16034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.16057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.16079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.16109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.16130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.16153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.16187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.16206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.16228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.16254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.16272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.16291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.16316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.16339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.16363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.16392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.16414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.16437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.16463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.16484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.16506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.16534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.16638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.16660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.16681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.16700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.16725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.16753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.16772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.16799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.16822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.16844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.16867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.16892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.16894s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.16897s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 1.2852029294034455 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20205037 bytes MEM: Free's : 26 free's of 20205037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-2: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 1.2852029294034455 is higher than threshold 0.5

[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Div_Const_439'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'Div_Const_439', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Div'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-2' pid=2382351 parent=2378264 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x6530eeaa8d60 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.108s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1413s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1415s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 5.410133314552377 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 21225069 bytes MEM: Free's : 26 free's of 21225069 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-2: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 5.410133314552377 is higher than threshold 0.5

[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Div_249'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'Div_249', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Div'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-3' pid=2382474 parent=2378489 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5c413e307d10 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.97s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2713s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2716s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 1430.8678615487806 MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18749771 bytes MEM: Free's : 27 free's of 18749771 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-3: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 1430.8678615487806 is higher than threshold 0.5

[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Div_212'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'Div_212', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Div'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-3' pid=2382630 parent=2378822 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5fa3450a7770 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.10613s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.11439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.11458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.11483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.11497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.11517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.11531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.11547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.11564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.11580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.11594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.11611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.11624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.11640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.11658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.11671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.11686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.11700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.11712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.11724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.11760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.11772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.11789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.11806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.11819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.11831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.11846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.11862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.11878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.11890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.11908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.11926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.11939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.11958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.11973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.11984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.11999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.12020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.12035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.12054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.12071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.12089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.12090s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.12092s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 80.48079382074071 MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 19043150 bytes MEM: Free's : 27 free's of 19043150 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-3: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 80.48079382074071 is higher than threshold 0.5

[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Div_Const_31'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'Div_Const_31', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Div'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-3' pid=2382785 parent=2378637 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x6126f62312b0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.112s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.21870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.21910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.21931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.21951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.21973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.21998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.21999s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.22004s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 1388.2031072784403 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 47516589 bytes MEM: Free's : 26 free's of 47516589 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-3: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 1388.2031072784403 is higher than threshold 0.5

[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Div_385'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'Div_385', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Div'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-3' pid=2382719 parent=2378283 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x6014722c1b40 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.75s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.6129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.6144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.6159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.6172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6673s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6675s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 347.40872776540834 MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 19767234 bytes MEM: Free's : 27 free's of 19767234 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-3: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 347.40872776540834 is higher than threshold 0.5

[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Div_81'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'Div_81', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Div'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-3' pid=2382832 parent=2378280 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x579909b8e760 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.66s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1385s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1387s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 2166.199113487146 MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18713703 bytes MEM: Free's : 27 free's of 18713703 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-3: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 2166.199113487146 is higher than threshold 0.5

[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Div_298'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'Div_298', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Div'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-3' pid=2382985 parent=2379051 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5a39963b4420 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.113s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.18272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.18298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.18325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.18345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.18370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.18390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.18416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.18442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.18459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.18478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.18501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.18520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.18545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.18570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.18592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.18614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.18635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.18656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.18677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.18700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.18721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.18743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.18763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.18782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.18805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.18824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.18842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.18861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.18884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.18904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.18930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.18949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.18971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.18989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.19011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.19031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.19062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.19088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.19111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.19137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.19162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.19164s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.19167s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 734.471140347928 MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18796028 bytes MEM: Free's : 27 free's of 18796028 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-3: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 734.471140347928 is higher than threshold 0.5

[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Div_89'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'Div_89', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Div'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-3' pid=2383173 parent=2378920 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5d84fac32150 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.3213s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.9156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.9188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.9201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.9222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.9232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.9245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.9258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.9269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.9284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.9295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.9307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.9320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.9330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.9341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.9353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.9365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9515s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9517s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 850.8369018615807 MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18929703 bytes MEM: Free's : 27 free's of 18929703 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-3: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 850.8369018615807 is higher than threshold 0.5

[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Div_384'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'Div_384', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Div'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-2' pid=2383409 parent=2378318 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x59b3e7cda2d0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.114s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6367s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6371s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 101.36681392285047 MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 19767234 bytes MEM: Free's : 27 free's of 19767234 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-2: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 101.36681392285047 is higher than threshold 0.5

[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Div_217'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'Div_217', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Div'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-4' pid=2383569 parent=2378489 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5c413e3083e0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.92s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3317s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3320s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 16.252743579839343 MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18699453 bytes MEM: Free's : 27 free's of 18699453 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-4: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 16.252743579839343 is higher than threshold 0.5

[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Div_329'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'Div_329', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Div'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-3' pid=2383568 parent=2378273 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x6103ffc776b0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.94s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2030s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2033s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 11.030788821710214 MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18734964 bytes MEM: Free's : 27 free's of 18734964 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-3: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 11.030788821710214 is higher than threshold 0.5

[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Div_373'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'Div_373', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Div'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-3' pid=2383670 parent=2378352 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5d1b69727b70 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.3s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.74s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5406s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5408s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 37.52770698154885 MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18766959 bytes MEM: Free's : 27 free's of 18766959 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-3: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 37.52770698154885 is higher than threshold 0.5

[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Div_306'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'Div_306', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Div'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-4' pid=2383684 parent=2378283 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x6014723ce1f0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.94s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.6525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.6566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.6591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.6606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7232s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7235s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 88.20789926410883 MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 19083356 bytes MEM: Free's : 27 free's of 19083356 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-4: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 88.20789926410883 is higher than threshold 0.5

[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Div_51'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'Div_51', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Div'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-3' pid=2383671 parent=2378264 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x6530eeaa95f0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.77s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3388s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3390s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 16187.847852763989 MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 21421301 bytes MEM: Free's : 27 free's of 21421301 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-3: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 16187.847852763989 is higher than threshold 0.5

[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Div_260'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'Div_260', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Div'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-3' pid=2384238 parent=2378788 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x647e07cec080 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.105s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.10341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.10366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.10394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.10415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.10444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.10466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.10605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.10631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.10653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.10679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.10700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.10724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.10744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.10774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.10825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.10848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.10867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.10886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.10908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.10928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.10948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.10971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.10993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.11012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.11034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.11056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.11078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.11097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.11117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.11139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.11162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.11182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.11201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.11220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.11239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.11258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.11286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.11305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.11327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.11349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.11375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.11377s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.11379s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 114.6303533463015 MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 19339952 bytes MEM: Free's : 27 free's of 19339952 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-3: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 114.6303533463015 is higher than threshold 0.5

[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Div_11'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'Div_11', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Div'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-4' pid=2384195 parent=2378920 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5d84fac2f8a0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.93s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.10144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.10167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.10184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.10199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.10212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.10225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.10237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.10254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.10265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.10277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.10288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.10301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.10311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.10327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.10340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.10354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10385s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10387s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 982.5817591150168 MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18811678 bytes MEM: Free's : 27 free's of 18811678 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-4: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 982.5817591150168 is higher than threshold 0.5

[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Div_179'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'Div_179', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Div'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-3' pid=2384237 parent=2378270 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x623e9e7dd560 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.82s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2599s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2601s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 378.2440619302366 MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18953139 bytes MEM: Free's : 27 free's of 18953139 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-3: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 378.2440619302366 is higher than threshold 0.5

[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Div_25'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'Div_25', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Div'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-4' pid=2384275 parent=2378280 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x579909aa7fe0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.110s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6754s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6756s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 41.916447510130375 MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 19551133 bytes MEM: Free's : 27 free's of 19551133 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-4: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 41.916447510130375 is higher than threshold 0.5

[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Div_252'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'Div_252', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Div'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-4' pid=2384386 parent=2379051 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5a39963bd330 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.86s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1808s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1810s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 43.74670973007314 MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18859760 bytes MEM: Free's : 27 free's of 18859760 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-4: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 43.74670973007314 is higher than threshold 0.5

[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Div_248'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'Div_248', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Div'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-5' pid=2384497 parent=2378822 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5fa345098e30 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.76s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1519s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1521s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 159.1842709528498 MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18739787 bytes MEM: Free's : 27 free's of 18739787 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-5: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 159.1842709528498 is higher than threshold 0.5

[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Div_403'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'Div_403', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Div'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-2' pid=2384796 parent=2378555 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5caba5ec7f20 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.97s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2113s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2116s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 15259.143243933937 MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18709226 bytes MEM: Free's : 27 free's of 18709226 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-2: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 15259.143243933937 is higher than threshold 0.5

[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Div_296'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'Div_296', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Div'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-4' pid=2384820 parent=2378986 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5cb99c20a3e0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.82s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1448s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1450s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 104.15515041073326 MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18794498 bytes MEM: Free's : 27 free's of 18794498 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-4: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 104.15515041073326 is higher than threshold 0.5

[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Div_Const_32'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'Div_Const_32', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Div'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-4' pid=2384905 parent=2378273 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x6103ff8c5f70 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.91s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1633s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1638s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 1757.435860685084 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 22520749 bytes MEM: Free's : 26 free's of 22520749 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-4: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 1757.435860685084 is higher than threshold 0.5

[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Div_436'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'Div_436', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Div'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-3' pid=2384904 parent=2378318 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x59b3e7e0a6b0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.111s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.12984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.13007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.13023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.13036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.13056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.13071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.13089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.13102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.13117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.13131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.13147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.13159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.13171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.13188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.13201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.13214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.13228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.13239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.13253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.13268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.13281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.13298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.13314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.13327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.13340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.13355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.13367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.13381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.13398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.13409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.13426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.13442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.13453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.13466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.13485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.13496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.13514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.13530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.13542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.13555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.13574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.13575s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.13577s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 17027.64984328844 MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 21443394 bytes MEM: Free's : 27 free's of 21443394 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-3: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 17027.64984328844 is higher than threshold 0.5

[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Div_Const_128'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'Div_Const_128', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Div'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-4' pid=2384903 parent=2378264 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x6530eeba4530 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.80s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1423s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1424s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 102.39024228288187 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18793389 bytes MEM: Free's : 26 free's of 18793389 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-4: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 102.39024228288187 is higher than threshold 0.5

[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Div_Const_425'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'Div_Const_425', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Div'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-5' pid=2384929 parent=2379184 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x588efaf38000 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.108s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4512s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4514s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 12.600956377742285 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19302958 bytes MEM: Free's : 26 free's of 19302958 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-5: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 12.600956377742285 is higher than threshold 0.5

[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Div_75'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'Div_75', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Div'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-4' pid=2384930 parent=2378753 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5c2eea1c8380 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.84s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5340s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5342s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 3.4049938246890052 MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18702651 bytes MEM: Free's : 27 free's of 18702651 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-4: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 3.4049938246890052 is higher than threshold 0.5

[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Div_359'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'Div_359', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Div'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-5' pid=2385149 parent=2378489 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5c413e30e220 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.76s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1470s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1471s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 33.262174969381235 MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18715764 bytes MEM: Free's : 27 free's of 18715764 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-5: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 33.262174969381235 is higher than threshold 0.5

[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Div_178'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'Div_178', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Div'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-5' pid=2385150 parent=2378920 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5d84fac41610 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.95s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1606s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1608s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 1526.814795395806 MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18973479 bytes MEM: Free's : 27 free's of 18973479 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-5: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 1526.814795395806 is higher than threshold 0.5

[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Div_Const_253'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'Div_Const_253', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Div'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-4' pid=2385367 parent=2379218 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x55cc7ef9cf00 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.86s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1389s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1391s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 84.11906926498675 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18849709 bytes MEM: Free's : 26 free's of 18849709 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-4: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 84.11906926498675 is higher than threshold 0.5

[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Div_191'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'Div_191', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Div'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-4' pid=2385707 parent=2378276 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x59dfe1ff5cd0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.118s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5783s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5786s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 4.527224911693462 MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18699317 bytes MEM: Free's : 27 free's of 18699317 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-4: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 4.527224911693462 is higher than threshold 0.5

[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Div_375'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'Div_375', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Div'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-6' pid=2385774 parent=2378267 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5972cc780970 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.106s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.13144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.13171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.13201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.13222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.13247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.13269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.13293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.13317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.13337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.13357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.13378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.13397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.13422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.13449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.13473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.13494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.13516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.13537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.13563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.13585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.13607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.13630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.13649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.13673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.13695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.13717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.13741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.13767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.13790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.13811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.13835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.13858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.13977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.13996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.14019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.14039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.14066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.14092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.14110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.14135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.14170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.14172s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.14174s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 4.557775802059301 MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18965364 bytes MEM: Free's : 27 free's of 18965364 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-6: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 4.557775802059301 is higher than threshold 0.5

[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Div_Const_381'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'Div_Const_381', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Div'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-6' pid=2385796 parent=2378822 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5fa3450ae7f0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.85s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2006s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2008s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 5.487021276862148 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18947949 bytes MEM: Free's : 26 free's of 18947949 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-6: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 5.487021276862148 is higher than threshold 0.5

[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Div_293'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'Div_293', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Div'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-4' pid=2385797 parent=2378270 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x623e9e7d5280 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.112s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1570s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1572s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 33.29667523455994 MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18794768 bytes MEM: Free's : 27 free's of 18794768 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-4: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 33.29667523455994 is higher than threshold 0.5

[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Div_313'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'Div_313', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Div'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-5' pid=2385969 parent=2378655 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x637853cfc110 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.107s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.12206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.12247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.12268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.12298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.12320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.12342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.12367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.12390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.12412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.12432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.12456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.12476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.12504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.12526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.12546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.12566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.12590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.12615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.12643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.12666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.12693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.12716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.12744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.12746s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.12750s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7934.678289729632 MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 20229404 bytes MEM: Free's : 27 free's of 20229404 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-5: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 7934.678289729632 is higher than threshold 0.5

[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Div_316'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'Div_316', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Div'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-5' pid=2385927 parent=2378986 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5cb99c2071f0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.68s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1481s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1483s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.9830014437534518 MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18699381 bytes MEM: Free's : 27 free's of 18699381 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-5: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 0.9830014437534518 is higher than threshold 0.5

[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Div_120'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'Div_120', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Div'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-5' pid=2386340 parent=2379051 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5a39963b89a0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.111s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.12504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.12538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.12564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.12592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.12619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.12642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.12667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.12690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.12710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.12736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.12761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.12781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.12807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.12834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.12858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.12881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.12907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.12930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.12951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.12974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.12996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.13020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.13039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.13059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.13083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.13104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.13126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.13145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.13167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.13189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.13217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.13237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.13262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.13281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.13306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.13326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.13354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.13377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.13400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.13423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.13458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.13461s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.13464s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 20.231647666552906 MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18730791 bytes MEM: Free's : 27 free's of 18730791 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-5: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 20.231647666552906 is higher than threshold 0.5

[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Div_407'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'Div_407', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Div'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-6' pid=2386334 parent=2378489 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5c413e3131f0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.87s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5078s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5080s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 23.229956123754455 MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18709886 bytes MEM: Free's : 27 free's of 18709886 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-6: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 23.229956123754455 is higher than threshold 0.5

[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Div_47'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'Div_47', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Div'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-4' pid=2386360 parent=2378788 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x647e083da530 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.80s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.10477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.10519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.10549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.10571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.10592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.10613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.10633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.10660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.10680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.10704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10759s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10763s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 6231587.807671275 MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 113070923 bytes MEM: Free's : 27 free's of 113070923 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-4: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 6231587.807671275 is higher than threshold 0.5

[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Div_Const_420'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'Div_Const_420', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Div'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-5' pid=2386336 parent=2379218 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x55cc7ef9ff50 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.89s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2758s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2761s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 4.590578316795285 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18843309 bytes MEM: Free's : 26 free's of 18843309 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-5: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 4.590578316795285 is higher than threshold 0.5

[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Div_Const_339'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'Div_Const_339', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Div'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-4' pid=2386335 parent=2379119 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5fc00af6bcc0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.70s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.8451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.8480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.8500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.8512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.8529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.8543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.8561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.8577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.8592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.8607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.8621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.8634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.8649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.8666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.8680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.8693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.8713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.8724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.8735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.8750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9031s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9033s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 10.771454443020586 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19255149 bytes MEM: Free's : 26 free's of 19255149 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-4: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 10.771454443020586 is higher than threshold 0.5

[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Div_Const_336'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'Div_Const_336', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Div'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-3' pid=2386532 parent=2378555 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5caba5edae70 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.98s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.15802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.15878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.15901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.15903s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.15907s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 4.704501084936932 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18839469 bytes MEM: Free's : 26 free's of 18839469 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-3: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 4.704501084936932 is higher than threshold 0.5

[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Div_Const_58'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'Div_Const_58', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Div'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-4' pid=2386536 parent=2378318 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x59b3e8fcd2a0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.88s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1442s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1444s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 5120.190230271441 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 148179885 bytes MEM: Free's : 26 free's of 148179885 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-4: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 5120.190230271441 is higher than threshold 0.5

[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Div_414'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'Div_414', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Div'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-5' pid=2386684 parent=2378264 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x6530eeba3380 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.111s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4674s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4677s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 27.8773031100893 MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18740294 bytes MEM: Free's : 27 free's of 18740294 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-5: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 27.8773031100893 is higher than threshold 0.5

[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Div_Const_81'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'Div_Const_81', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Div'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-6' pid=2386685 parent=2379184 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x588efb0288b0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.107s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2180s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2182s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 2.684357408380855 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18695245 bytes MEM: Free's : 26 free's of 18695245 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-6: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 2.684357408380855 is higher than threshold 0.5

[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Div_58'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'Div_58', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Div'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-5' pid=2386683 parent=2378273 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x6103ffc7e720 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.97s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.11996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.12033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.12059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.12088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.12109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.12130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.12157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.12177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.12196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.12218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.12238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.12257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.12284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.15953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.15990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.16020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.16044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.16068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.16091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.16120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.16145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.16170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.16191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.16220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.16243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.16267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.16292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.16316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.16336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.16371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.16391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.16414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.16438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.16467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.16487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.16518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.16538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.16561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.16589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.16618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.16620s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.16623s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 1109439.1469112781 MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 159732825 bytes MEM: Free's : 27 free's of 159732825 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-5: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 1109439.1469112781 is higher than threshold 0.5

[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Div_216'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'Div_216', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Div'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-6' pid=2387098 parent=2378986 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5cb99c20bef0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.105s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1951s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1953s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.369024436533233 MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18699390 bytes MEM: Free's : 27 free's of 18699390 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-6: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 7.369024436533233 is higher than threshold 0.5

[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Div_243'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'Div_243', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Div'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-5' pid=2387099 parent=2378270 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x623e9e7d5790 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.86s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1742s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1744s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 79.54741377811358 MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18739472 bytes MEM: Free's : 27 free's of 18739472 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-5: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 79.54741377811358 is higher than threshold 0.5

[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Div_99'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'Div_99', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Div'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-7' pid=2387100 parent=2378283 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x6014723b9240 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.66s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1463s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1465s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 1.0221030820359904 MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18699577 bytes MEM: Free's : 27 free's of 18699577 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-7: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 1.0221030820359904 is higher than threshold 0.5

[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Div_Const_90'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'Div_Const_90', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Div'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-7' pid=2387276 parent=2378489 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5c413e32c540 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.82s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1474s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1476s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 26.78926345304407 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18934701 bytes MEM: Free's : 26 free's of 18934701 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-7: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 26.78926345304407 is higher than threshold 0.5

[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Div_60'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'Div_60', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Div'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-6' pid=2387643 parent=2379218 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x55cc7efa0780 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.88s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.19080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.19118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.19146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.19167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.19191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.19212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.19233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.19253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.19282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.19307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.19327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.19349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.19369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.19390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.19421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.19443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.19468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.19496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.19520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.19522s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.19528s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 142071.17881170634 MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 134101943 bytes MEM: Free's : 27 free's of 134101943 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-6: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 142071.17881170634 is higher than threshold 0.5

[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Div_337'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'Div_337', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Div'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-6' pid=2387771 parent=2378655 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x637853cff7b0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.84s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1493s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1495s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 4.052859147061499 MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 19272564 bytes MEM: Free's : 27 free's of 19272564 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-6: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 4.052859147061499 is higher than threshold 0.5

[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Div_322'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'Div_322', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Div'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-7' pid=2388115 parent=2378753 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5c2eea1d0d40 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.93s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.6093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.6149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.6164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.6182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6764s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6767s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 2.6783223977169897 MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18701546 bytes MEM: Free's : 27 free's of 18701546 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-7: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 2.6783223977169897 is higher than threshold 0.5

[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Div_142'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'Div_142', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Div'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-7' pid=2388178 parent=2379184 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x588efb02bf10 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.104s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2771s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2774s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 3.730254669689703 MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18699733 bytes MEM: Free's : 27 free's of 18699733 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-7: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 3.730254669689703 is higher than threshold 0.5

[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Div_278'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'Div_278', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Div'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-8' pid=2388179 parent=2378489 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5c413e318b20 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.107s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.22235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.22265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.22294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.22318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.22347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.22372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.22392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.22413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.22438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.22460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.22479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.22498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.22518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.22542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.22565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.22589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.22612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.22630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.22651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.22675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.22707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.22732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.22759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.22780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.22805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.22828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.22851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.22875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.22894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.22919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.22945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.22964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.22991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.23011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.23032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.23057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.23086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.23106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.23133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.23157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.23186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.23188s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.23190s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 213.90746240538454 MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18705224 bytes MEM: Free's : 27 free's of 18705224 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-8: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 213.90746240538454 is higher than threshold 0.5

[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Div_Const_260'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'Div_Const_260', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Div'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-6' pid=2388203 parent=2378264 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x6530eeab7a80 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.297s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.40320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.40348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.40368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.40387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.40413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.40435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.40460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.40482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.40504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.40525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.40544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.40563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.40588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.40617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.40638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.40660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.40681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.40703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.40731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.40753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.40773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.40799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.40822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.40841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.40868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.40896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.40920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.40944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.40966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.40987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.41019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.41038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.41059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.41082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.41104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.41125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.41153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.41172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.41193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.41222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.41249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.41251s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.41253s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.6288446092695946 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19320301 bytes MEM: Free's : 26 free's of 19320301 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-6: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 0.6288446092695946 is higher than threshold 0.5

[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Div_332'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'Div_332', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Div'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-6' pid=2388340 parent=2379051 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5a39963bc150 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.145s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3413s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3416s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 1105.8657737463677 MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18746434 bytes MEM: Free's : 27 free's of 18746434 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-6: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 1105.8657737463677 is higher than threshold 0.5

[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Div_Const_46'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'Div_Const_46', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Div'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-8' pid=2388463 parent=2378283 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x6014723bb1a0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.3s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.72s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1329s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1331s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 1706.705480396381 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 103615405 bytes MEM: Free's : 26 free's of 103615405 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-8: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 1706.705480396381 is higher than threshold 0.5

[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Div_Const_136'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'Div_Const_136', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Div'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-7' pid=2388528 parent=2378920 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5d84fab4ea10 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.86s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1600s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1603s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 32.13943987427616 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19131309 bytes MEM: Free's : 26 free's of 19131309 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-7: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 32.13943987427616 is higher than threshold 0.5

[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Div_251'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'Div_251', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Div'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-7' pid=2388529 parent=2378352 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5d1b69739ce0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.113s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.29704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.29764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.29789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.29818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.29846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.29875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.29899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.29926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.29948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.29974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.30004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.30037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.30060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.30091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.30117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.30142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.30145s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.30149s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 529.691533136052 MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18859760 bytes MEM: Free's : 27 free's of 18859760 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-7: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 529.691533136052 is higher than threshold 0.5

[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Div_347'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'Div_347', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Div'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-6' pid=2388530 parent=2379119 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5fc00b05ccf0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.66s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1322s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1325s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 2.499357088862131 MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18700255 bytes MEM: Free's : 27 free's of 18700255 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-6: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 2.499357088862131 is higher than threshold 0.5

[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Div_318'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'Div_318', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Div'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-9' pid=2388596 parent=2378822 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5fa3450a2110 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.88s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1442s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1444s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 13.430472770714829 MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18699742 bytes MEM: Free's : 27 free's of 18699742 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-9: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 13.430472770714829 is higher than threshold 0.5

[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Div_Const_331'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'Div_Const_331', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Div'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-7' pid=2388817 parent=2378486 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x6020243382d0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.109s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1489s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1491s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 60.588563604005984 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18716925 bytes MEM: Free's : 26 free's of 18716925 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-7: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 60.588563604005984 is higher than threshold 0.5

[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Div_388'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'Div_388', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Div'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-4' pid=2388815 parent=2378637 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x6126f642a0e0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.89s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1495s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1497s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 1093.710867041409 MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 19769199 bytes MEM: Free's : 27 free's of 19769199 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-4: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 1093.710867041409 is higher than threshold 0.5

[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Div_275'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'Div_275', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Div'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-5' pid=2389153 parent=2378555 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5caba5ed39d0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.157s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4457s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4462s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 995.2780328988355 MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18701024 bytes MEM: Free's : 27 free's of 18701024 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-5: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 995.2780328988355 is higher than threshold 0.5